PEB 2091
PEF 2091
Register Description
MX bit - are stored. Additionally, an active MRC enables the control of the MR handshake
bit according to the Monitor channel protocol.
5.2
Detailed Register Description
5.2.1
ISTA-Register
Read
Address 0
H
The Interrupt Status Register (ISTA) generates an interrupt for the selected channel.
Interrupt bits are cleared by reading the corresponding register.
Reset value: 00H
7
6
5
4
3
2
1
0
D
CICI
CICU
SF
MDR
B1
B2
MDA
D
D-channel Interrupt
1=
Indicates an interrupt that 8 bits D-channel data have been updated
0=
Occurs after DRI and DRU have been read
CICI
CICU
SF
C/I-channel Interrupt IOM®-2
1=
0=
Indicates a change in the C/I-channel on IOM®-2
Occurs after CIRI is read
C/I-channel Interrupt U
1=
0=
Indicates a change in the C/I-channel coming from the transceiver core
Occurs after CIRU is read
Superframe Marker
1=
0=
Indicates a superframe marker received from the transceiver core
Occurs when the ISTA-Register has been read
Monitor Data Receive Interrupt
MDR
1=
0=
Indicates an interrupt after the MOSR:MDR or the MOSR:MER bits
have been activated
Indicates the inactive interrupt status
B1
B1-channel Interrupt
1=
0=
Indicates an interrupt every time B1-channel bytes arrive
Occurs after RB1I and RB1U have been read
Semiconductor Group
210
Data Sheet 01.99
INFINEON [ Infineon ]
