PEB 2091
PEF 2091
Operational Description
Table 33
S/G Bit Control Overview
SWST: SWST: ADF: Description
Application
BS
SGL
CBAC
x1)
0
0
0
1
S/G bit always "0"
S/G bit always "1"
(default)
0
S/G and BAC are
handled by other
devices than the IEC-Q
0
1
1
1
0
0
1
0
1
S/G bit set to "1" continuously with ELIC® on linecard,
EOC 25H received, reset to "0"
with EOC 27H received
BAC bit controls S/G-bit,
Interframe fill of
terminals contains
zeroes
upstream D-channel not affected (e.g. ’01111110’)
S/G bit set to "1" for 4
Synchronization of
base station, e.g. IBMC
or MBMC
IOM®-2-frames with EOC 25H
received, automatically reset to
"0" after that. This is the default
setting of ADF:CBAC after reset
S/G bit set to "0" for 4
IOM®-2-frames with EOC 25H
received, automatically reset to
"1" after that
Synchronization of
base station, e.g. IBMC
or MBMC. Inverse
polarity to the setting
1,0,0 (last row)
1
1
1
1
0
1
S/G bit set to "1" continuously with
EOC 25H received, reset to "0"
with EOC 27H received
BAC bit not read by IEC-Q V 5.3
S/G bit set to "1" continuously with ELIC® on linecard,
EOC 25H received, reset to "0"
with EOC 27H received
Interframe fill of
terminals are ’ones’
BAC bit controls upstream
D-channel and S/G-bit
1) ’x’ is don’t care
Semiconductor Group
199
Data Sheet 01.99
INFINEON [ Infineon ]
