PEB 2091
PEF 2091
Operational Description
Signals on U-Interface
The signals SLx, TL and SP transmitted on the U-interface are defined in Table 28, page
125. The polarity of the overhead bits ACT and DEA is indicated as follows:
a = 0/1 corresponds to ACT bit set to binary "0/1".
d = 0/1 corresponds to DEA bit set to binary "0/1".
The polarity of the transmitted UOA-bit depends on the received C/I-channel code:
– UAR sets UOA-bit to binary 0.
– AR sets UOA-bit to binary 1.
– Any other C/I-codes sets the UOA to the same value as the received SAI bit. After
deactivation the UOA-bit is set to binary 0 until a valid SAI-bit is received.
4.4.2.4 LT States
This section describes the functions of all states defined in LT modes.
Alerting
The wake-up signal TL is transmitted for 3 ms (T2) in response to an activation request
from the LT side (AR, AR0, UAR or ARL). In the case of an analog loop-back, the signal
TL is forwarded internally to the wake-up signal detector and stored.
Awake
If the C/I command is issued in the Deactivated state the Awake state is entered upon
the receipt of a wake-up or an acknowledge signal TN from the NT. In the case of an
activation started by the LT side, timer T1 is restarted when the "Awake" state is entered.
Awake Error
The "Awake Error" state is equivalent to the "Awake" state, but is entered only when a
wake-up signal is received while being in the "Receive reset" state. As the "Receive
reset" state was entered upon the application of the C/I-channel code RES1, the "Awake
error" state assures that a minimum amount of time elapses between the application of
the RES1-code and the IEC-Q entering a state (EQ training) in which it again reacts on
the RES1-code. The LT side is requested to stop issuing the command RES1 within T9
after the receipt of the C/I-channel code AR on DOUT and to replace it by another
command such as the idle code DC for instance.
Semiconductor Group
156
Data Sheet 01.99
INFINEON [ Infineon ]
