PEB 2091
PEF 2091
Operational Description
U Basic Frame
1.5 ms
Transmitter
Data
(I)SW
Fixed
18 Bits
Data
12x (2B+D)
216 Bits
M1-M3
3 Bits
M4
1 Bit
M5-M6
2 Bit
(To U)
MON-0
From IOM®-2
or µP
Time
EOC
Processor
Figure 48
Access to EOC Transmission on U
U Basic Frame
1.5 ms
Receiver
Data
(From U)
Data
12x (2B+D)
216 Bits
(I)SW
Fixed
18 Bits
M5-M6
2 Bit
M4
1 Bit
M1-M3
3 Bits
Time
MON-0
To IOM®-2 and
µP (if used)
EOC
Processor
Figure 49
Access to EOC Received from U
In other states the EOC-processor clamps all EOC-maintenance bits to high when
EOC-bits are transmitted.
The address bits, d/m bit and the EOC code of the two byte MON-0 message (see Table
18 below) corresponds to the address bits , d/m bits and EOC code in the EOC channel
of the U-interface (see "U-Frame Structure", page 68). For more information on Monitor
Channel handling, see "IOM®-2 Monitor Channel", page 76 and for the microprocessor
mode "Monitor Channel Access", page 101. For a complete list of the available Monitor
Channel commands, see "MON-0 Codes", page 226.
Table 18
Content of MON-0 Message
1. Byte
2. Byte
0 0 0 0
MON-0
A A A | 1
E E E E
E E E E
Addr. | d/m
EOC Code
Semiconductor Group
111
Data Sheet 01.99
INFINEON [ Infineon ]
