Functional Description
An access request to the TIC bus may either be generated by software (µP access to the C/I
channel) or by the ISAC-S itself (transmission of an HDLC frame). A software access request
to the bus is effected by setting the BAC bit (CIXR register) to "1".
In case of an access request, the ISAC-S checks the bus accessed-bit (bit 3 of IDP1
MONITOR octet, see figure 25) for the status "bus free", which is indicated by a logical "1". If
the bus is free, the ISAC-S transmits its individual TIC bus address programmed in STCR
register. The TIC bus is occupied by the device which sends its address error-free. If more than
one device attempts to seize the bus simultaneously, the one with the lowest address value
wins.
7
6
5
4
3
2
1
0
TIC Bus Address TBA2-0
Bus accessed = "1" (no TIC bus access) if
– BAC = "0" (CIXR register) and
– no HDLC transmission
Figure 25
MONITOR Channel Structure on IDP1
When the TIC bus is seized by the ISAC-S, the bus is identified to other devices as occupied
via the IDP1 MONITOR channel bus accessed bit state "0" until the access request is
withdrawn. After a successful bus access, the ISAC-S is automatically set into a lower priority
class, that is, a new bus access cannot be performed until the status "bus free" is indicated in
two successive frames.
If none of the devices connected to the IOM interface request access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will therefore
have access, by default, to the D and C/I channels.
Note: Bit BAC (CIXR register) should be reset by the µP when access to the C/I channels is
no longer requested, to grant other devices access to the D and C/I channels.
The availability of the S/T interface D channel is indicated in bit 3 "Stop/Go" (S/G) of the IDP0
MONITOR channel (figure 26).
S/G = 1 : stop
S/G = 0 : go
7
6
5
4
3
2
1
0
1
1
1
1
S/G
1
1
1
Figure 26
MONITOR Channel on IDP0
The stop/go bit is available to other layer-2 devices connected to the IOM to determine if they
can access the S/T bus D channel.
Semiconductor Group
57
INFINEON [ Infineon ]
