PEB 2086
1.2.2
Logic Symbol of PEB 2086
± 100 ppm
Reset 7.68 MHz
+ 5 V 0 V
0 V
VDD VSSA VSSD RST
IDP0
XTAL1
XTAL2
SR2
R
IOM
*)
IDP1
TR = 100 Ω
SR1
SDAX/SDS1
SDAR
SSI
S/T
SX2
SX1
SIP/EAW
DCL
SLD
*)
TR = 100 Ω
FSC1
Clock Frame
Synchronization
CP/BCL
Mode
M0...1
X1...2
Special
Function
Pins
SCA/FSD/SDS2
FSC2
AD0...7
(D0...7) (A0...5)
WR
(R/W) (DS)
RD
CS
INT ALE
P
µ
*)
Terminating resistors only at the far ends of the connection
ITL03792
Figure 2
Logic Symbol of the ISAC®-S
Semiconductor Group
23