Functional Description
set), the CPU can write a data block of up to 32 bytes to the transmit FIFO. After this, data
transmission can be initiated by command.
Two different frames types can be transmitted:
– Transparent frame (command: XTF), or
– I frames (command: XIF)
as shown in figure 60.
For transparent frames, the whole frame including address and control field must be written to
the XFIFO.
HDLC Frame
Flag
Flag
Flag
Flag
Address
XAD1
Control
Control
Control
Information
XFIFO
CRC
CRC
CRC
CRC
Flag
Flag
Flag
Flag
Transmit I-Frame
(XIF)
Auto Mode, 8-Bit Addr.
Transmit I-Frame
(XIF)
Auto-Mode, 16-Bit Addr.
XAD1 XAD2
XFIFO
Transmit Transparent
Frame (XTF)
XFIFO
All Modes
Note: Length of Control Field is b or 16 Bit
Description of Symbols:
Generated automatically by ISAC R -S
Written initially by CPU (Info Register)
Loaded (repeatedly) by CPU upon ISAC R -S
request (XPR Interrupt)
ITD02341
Figure 60
Transmitter Data Flow
The transmission of I frames is possible only if the ISAC-S is operating in the auto-mode. The
address and control field is autonomously generated by the ISAC-S and appended to the
frame, only the data in the information field must be written to the XFIFO.
If a 2 byte address field has been selected, the ISAC-S takes the contents of the XAD 1 register
to build the high byte of the address field, and the contents of the XAD 2 register to build the
low byte of the address field.
Additionally the C/R bit (bit 1 of the high byte address, as defined by LAPD protocol) is set to
"1" or "0" dependent on whether the frame is a command or a response.
Semiconductor Group
115
INFINEON [ Infineon ]
