Functional Description
Information about the received frame is available for theµP when a RME interrupt is generated,
as shown in table 8.
Table 8
Receive Information at RME Interrupt
Information
Register (adr. Bit
hex)
Mode
First byte after flag
(SAPI of LAPD
address field)
SAPR
(26) –
Transparent mode 1
Control field
RHCR (29) –
Auto mode, I (modulo 8) and U frames
Auto mode, I frames (modulo 128)
Non-auto mode, 1-byte address field
Compressed control field RHCR (29) –
2nd byte after flag
3rd byte after flag
RHCR (29) –
RHCR (29) –
Non-auto mode, 2-byte address field
Transparent mode 1
Type of frame
(Command/Response)
RSTA
RSTA
(27) C/R
Auto mode, 2 byte address field
Non-auto mode, 2-byte address field
Transparent mode 3
Recognition of SAPI
(27) SA1-0
Auto mode, 2 byte address field
Non-auto mode, 2-byte address field
Transparent mode 3
Recognition of TEI
RSTA
(27) TA
All except transparent modes 2, 3
Result of CRC check
(correct/incorrect)
RSTA
(27) CRC
ALL
Data available in RFIFO
(yes/no)
RSTA
(27) RDA
(27) RAB
(27) RDO
ALL
ALL
ALL
Abort condition detected RSTA
(yes/no)
Data overflow during
reception of a frame
(yes/no)
RSTA
Number of bytes received RBCL
in RFIFO
(25) RBC4-0 ALL
(25) RBC11-0 ALL
Message length
RBCL
RBCH (2A) OV
2.8.4
Transmission of Frames
A 2 × 32 byte FIFO buffer (transmit pools) is provided in the transmit direction.
If the transmit pool is ready (which is true after an XPR interrupt or if the XFW bit in STAR is
Semiconductor Group
114
INFINEON [ Infineon ]
