Functional Description
Only the logical connection identified through the address combination SAP1, TEI1 will be
processed in the auto mode, all others are handled as in the non-auto mode. The logical
connection handled in the auto mode must have a window size 1 between transmitted and
acknowledged frames. HDLC frames with address fields that do not match with any of the
address combinations, are ignored by the ISAC-S.
In case of a 1-byte address, TEI1 and TEI2 will be used as compare registers. According to
the X.25 LAPB protocol, the value in TEI1 will be interpreted as command and the value in
TEI2 as response.
The control field is stored in the RHCR register and the I field in the RFIFO. Additional
information is available in the RSTA.
Non-auto mode (MDS2, MDS1 = 01)
Characteristics:
Full address recognition (1 or 2 bytes)
Arbitrary window sizes
All frames with valid addresses (address recognition identical to auto mode) are accepted and
the bytes following the address are transferred to the µP via RHCR and RFIFO. Additional
information is available in the RSTA.
Transparent mode 1 (MDS2, MDS1, MDS0 = 101)
Characteristics:
TEI recognition
A comparison is performed only on the second byte after the opening flag, with TEI1, TEI2 and
group TEI (FF ). In the case of a match, the first address byte is stored in SAPR, the (first byte
H
of the) control field in RHCR, and the rest of the frame in the RFIFO. Additional information is
available in the RSTA.
Transparent mode 2 (MDS2, MDS1, MDS0 = 110)
Characteristics:
no address recognition
Every received frame is stored in the RFIFO (first byte after opening flag to CRC field).
Additional information can be read from the RSTA.
Transparent mode 3 (MDS2, MDS1, MDS0 = 111)
Characteristics:
SAPI recognition
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and group
SAPI (FE/FC ). In the case of a match, all the following bytes are stored in RFIFO. Additional
H
information can be read from the RSTA.
2.8.2
Protocol Operations (auto mode)
In addition to address recognition all S and I frames are processed in hardware in the auto
mode. The following functions are performed:
– update of transmit and receive counter
– evaluation of transmit and receive counter
Semiconductor Group
109
INFINEON [ Infineon ]
