IN16C1054
6.5.2 Block DMA transfer (DMA Mode 1)
Transmitter: When the characters in TX FIFO are less than the trigger level that is set in
TTR, TXRDY# or TXRDY[3:0] signal is asserted. When TX FIFO is full, TXRDY# or
TXRDY[3:0]# signal is deasserted.
Receiver: When the characters in RX FIFO are more than the trigger level that is set in
RTR, RXRDY# or RXRDY[3:0] signal is asserted. When RX FIFO is empty, RXRDY# or
RXRDY[3:0]# signal is deasserted.
The figure 6 below shows TXRDY#, TXRDY[3:0]# and RXRDY#, RXRDY[3:0]# in DMA
mode 1.
TX FIFO
RX FIFO
Character #256
Character #255
EMPTY
SPACE
TTR
80h
RTR
80h
TXRDY#,
TXRDY[3:0]#
RXRDY#,
RXRDY[3:0]#
Character #128
Character #127
Character #128
Character #127
Character #2
Character #1
Character #2
Character #1
TCR
00h
RCR
80h
ISR[7]
0
ISR[6]
0
TX FIFO FULL
EMPTY
SPACE
RXRDY#,
RXRDY[3:0]#
TTR
80h
RTR
80h
TXRDY#,
TXRDY[3:0]#
Character #128
Character #127
Character #2
Character #1
TCR
80h
RCR
00h
ISR[7]
0
ISR[6]
0
RX FIFO EMPTY
Figure 6: TXRDY#/TXRDY[3:0]# and RXRDY#/RXRDY[3:0]# in DMA mode 1.
6.6 Sleep Mode with Auto Wake-Up
The SB16C1054 provides sleep mode operation to reduce its power consumption when
sleep mode is activated. Sleep mode is enabled when EFR[4] and IER[4] are set to ‘1’.
Sleep mode is activated when:
■
■
■
■
RXD input is in idle state.
CTS#, DSR#, DCD#, and RI# are not toggling.
The TX FIFO and TSR are in empty state.
No interrupt is pending except THR and time-out interrupts.
In sleep mode, the SB16C1054 clock and baud rate clock are stopped. Since most
registers are clocked using these clocks, the power consumption is greatly reduced.
Normal operation is resumed when:
■
■
■
RXD input receives the data start bit transition.
Data byte is loaded to the TX FIFO or THR.
CTS#, DSR#, DCD#, and RI# inputs are changed.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
