IN16C1054
6.5 DMA Operation
Transmitter and Receiver DMA operation is available through TXRDY#, RXRDY#,
TXRDY[3:0]#, and RXRDY[3:0]#. There are two modes of DMA operation, DMA mode 0
or DMA mode 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[3] = 0), DMA occurs in single character transfer. In
DMA mode 1, multi-character DMA transfers are managed to relieve the CPU for longer
periods of time.
6.5.1 Single DMA transfer (DMA Mode 0/FIFO Disable)
Transmitter: There are no character in TX FIFO or THR. And the TXRDY# and
TXRDY[3:0]# signals will be in assert state. TXRDY#, TXRDY[3:0]# will switch to deassert
state after one character is loaded into TX FIFO or THR.
Receiver: There is at least one character in RX FIFO or RHR. And the RXRDY# and
RXRDY[3:0]# signals will be in assert state. Once RXRDY# is asserted, RXRDY[3:0]#
signal will switch to deassert state when there are no more characters in RX FIFO or
RBR.
Figure 5 shows TXRDY#, TXRDY[3:0]#, RXRDY#, and RXRDY[3:0]# in DMA mode
0/FIFO disable.
TX FIFO
RX FIFO
TXRDY#,
TXRDY[3:0]#
RXRDY#,
RXRDY[3:0]#
EMPTY
SPACE
EMPTY
SPACE
TCR
01h
RCR
01h
ISR[7]
0
ISR[6]
0
AT LEAST ONE
LOCATION FILLED
AT LEAST ONE
LOCATION FILLED
Character #1
Character #1
RXRDY#,
RXRDY[3:0]#
TXRDY#,
TXRDY[3:0]#
TCR
00h
RCR
00h
ISR[7]
1
ISR[6]
0
TX FIFO EMPTY
RX FIFO EMPTY
Figure 5: TXRDY#/TXRDY[3:0]# and RXRDY#/RXRDY[3:0]# in DMA mode 0/FIFO disable.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
