IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
WRITE CLOCK
READ CLOCK
READ CHIP SELECT
READ ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
RCS
REN
WRITE ENABLE
INPUT READY
IDT
IDT
OR
WEN
72T7285
72T7295
72T72105
72T72115
72T7285
72T7295
72T72105
72T72115
REN
RCS
OUTPUT READY
IR
OR
OE
OUTPUT ENABLE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5994 drw42
Figure 37. Block Diagram of 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T7285caneasilybe adaptedtoapplications requiringdepths
greaterthan16,384,32,768fortheIDT72T7295,65,536fortheIDT72T72105
and131,072fortheIDT72T72115withan72-bitbuswidth.InFWFTmode,
theFIFOscanbeconnectedinseries(thedataoutputsofoneFIFOconnected
tothedatainputsofthenext)withnoexternallogicnecessary. Theresulting
configuration provides a total depth equivalent to the sum of the depths
associatedwitheachsingleFIFO. Figure37showsadepthexpansionusing
twoIDT72T7285/72T7295/72T72105/72T72115devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethe
datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,
enabling a write to the next FIFO in line.
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
52
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