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IDT72T7295L7BBI 参数 Datasheet PDF下载

IDT72T7295L7BBI图片预览
型号: IDT72T7295L7BBI
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5 VOLT HIGH -SPEED TeraSyncTM FIFO 72位配置 [2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 536 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync  
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72  
                                                                                                                              
72-BIT FIFO  
                                                                                                                              
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
avoidedbycreatingcomposite flags, thatis, ANDingEF ofeveryFIFO, and  
separately ANDing FF of every FIFO. In FWFT mode, composite flags can  
be created by ORing OR of every FIFO, and separately ORing IR of every  
FIFO.  
Figure 36 demonstrates a width expansion using two IDT72T7285/  
72T7295/72T72105/72T72115 devices. D0 - D71 from each device form a  
144-bitwideinputbusandQ0-Q71fromeachdeviceforma144-bitwideoutput  
bus. Any word width can be attained by adding additional IDT72T7285/  
72T7295/72T72105/72T72115devices.  
OPTIONALCONFIGURATIONS  
WIDTH EXPANSION CONFIGURATION  
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control  
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.  
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR  
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK  
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary  
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe  
SERIAL CLOCK (SCLK)  
PARTIAL RESET (PRS)  
MASTER RESET (MRS)  
FIRST WORD FALL THROUGH/  
SERIAL INPUT (FWFT/SI)  
RETRANSMIT (RT)  
Dm+1 - Dn  
m + n  
m
n
D0 - Dm  
DATA IN  
READ CLOCK (RCLK)  
READ CHIP SELECT (RCS)  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN)  
LOAD (LD)  
READ ENABLE (REN)  
IDT  
IDT  
72T7285  
72T7295  
OUTPUT ENABLE (OE)  
72T7285  
72T7295  
72T72105  
72T72115  
PROGRAMMABLE (PAE)  
72T72105  
#1  
FULL FLAG/INPUT READY (FF/IR)  
72T72115  
(1)  
GATE  
EMPTY FLAG/OUTPUT READY (EF/OR) #1  
(1)  
FULL FLAG/INPUT READY (FF/IR) #2  
GATE  
EMPTY FLAG/OUTPUT READY (EF/OR) #2  
FIFO  
#2  
m + n  
PROGRAMMABLE (PAF)  
HALF-FULL FLAG (HF)  
n
FIFO  
#1  
Qm+1 - Qn  
DATA OUT  
m
5994 drw41  
Q0 - Qm  
NOTES:  
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.  
2. Do not connect any output control signals directly together.  
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.  
Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion  
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