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IDT71V016SA12PHGI8 参数 Datasheet PDF下载

IDT71V016SA12PHGI8图片预览
型号: IDT71V016SA12PHGI8
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 9 页 / 98 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT71V016SA, 3.3V CMOS Static RAM  
1 Meg (64K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
tAS  
tCW  
tBW  
BHE, BLE  
tWP  
tWR  
WE  
DATAOUT  
DATAIN  
tDH  
tDW  
DATAIN VALID  
3834 drw 09  
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
tCW  
tAS  
tBW  
BHE, BLE  
tWP  
tWR  
WE  
DATAOUT  
DATAIN  
tDH  
tDW  
DATAIN VALID  
3834 drw 10  
NOTES:  
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.  
2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed  
onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.  
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.  
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.  
5. Transitionismeasured±200mVfromsteadystate.  
6.42  
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