IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
BE
t
BLZ
(1)
t
BHZ
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
Parameter
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
71V016SA10
(2)
Min.
Max.
71V016SA12
Min.
Max.
71V016SA15
Min.
Max.
71V016SA20
Min.
Max.
Unit
10
____
____
____
12
____
____
____
15
____
____
____
20
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
____
12
12
____
15
15
____
20
20
____
4
____
4
____
5
____
5
____
5
5
____
6
6
____
6
7
____
8
8
____
____
____
____
____
0
____
0
____
0
____
0
____
5
—
5
____
6
—
6
____
6
—
7
____
8
—
8
____
4
—
0
____
4
—
0
____
4
—
0
____
4
____
0
____
5
6
6
8
WRITE CYCLE
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Lo w to End of Write
Byte Enable Lo w to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
10
7
7
7
0
0
7
5
0
3
____
____
____
12
8
8
8
0
0
8
6
0
3
____
____
____
15
10
10
10
0
0
10
7
0
3
____
____
____
20
12
12
12
0
0
12
9
0
3
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3834 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
6
6
8
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 0°C to +70°C temperature range only.
Timing Waveform of Read Cycle No. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3834 drw 06
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE, BHE,
and
BLE
are LOW.
6.42
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
