IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(2,4,5)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY(M/S = VIH
)
tWC
MATCH
ADDR"A"
R/W"A"
t
WP
t
DW
t
DH
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
2738 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
TIMING WAVEFORM OF WITH WRITE BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
2738 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
6.06
13
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
