IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
t
AW
(9)
CE or SEM
(2)
tWP
(3)
(6)
tWR
tAS
R/W
DATAOUT
DATAIN
(7)
t
OW
tWZ
(4)
(4)
tDW
tDH
2738 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
t
WC
ADDRESS
CE or SEM (9)
R/W
tAW
(6)
AS
(3)
WR
(2)
tEW
t
t
tDW
tDH
DATAIN
2738 drw 10
NOTES:
1. R/W or CE must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mv from steady state with the Output
Test Load (Figure 2).
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIH and SEM = VIL. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.06
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
