IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER
CE
SLAVE
CE
Dual Port
RAM
Dual Port
RAM
BUSY
R
BUSY
L
BUSY
L
BUSYR
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
BUSY
R
BUSY
L
BUSYL
BUSY
R
R
BUSY
L
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Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
output from the master before the actual write pulse can be
The use of busy logic is not required or desirable for all initiatedwiththeR/Wsignal. Failuretoobservethistimingcan
applications. In some cases it may be useful to logically OR result in a glitched internal write inhibit signal and corrupted
the busy outputs together and use any busy indication as an data in the slave.
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/Spin. Once in slave mode theBUSY
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
SEMAPHORES
The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS
Static RAM with an additional 8 address locations dedicated
tobinarysemaphoreflags. Theseflagsalloweitherprocessor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
The busy outputs on the IDT 7005 RAM in master mode,
can be used by one processor to inhibit the other from
are push-pull type outputs and do not require pull up resistors
accessing a portion of the Dual-Port RAM or any other shared
to operate. If these RAMs are being expanded in depth, then
resource.
the busy indication for the resulting array requires the use of
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
an external AND gate.
that the activity on the left port in no way slows the access time
oftherightport. Bothportsareidenticalinfunctiontostandard
CMOS Static RAM and can be read from, or written to, at the
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7005 RAM array in width while same time with the only possible conflict arising from the
using busy logic, one master part is used to decide which side simultaneous writing of, or a simultaneous READ/WRITE of,
of the RAM array will receive a busy indication, and to output anon-semaphorelocation. Semaphoresareprotectedagainst
that indication. Any number of slaves to be addressed in the such ambiguous situations and may be used by the system
same address range as the master, use the busy signal as a program to avoid any conflicts in the non-semaphore portion
write inhibit signal. Thus on the IDT7005 RAM the busy pin is of the Dual-Port RAM. These devices have an automatic
an output if the part is used as a master (M/Spin = H), and the power-down feature controlled by CE, the Dual-Port RAM
busy pin is an input if the part used as a slave (M/Spin = L) as enable, and SEM, the semaphore enable. The CE and SEM
shown in Figure 3.
pins control on-chip power down circuitry that permits the
If two or more master parts were used when expanding in respective port to go into standby mode when not selected.
width, a split decision could result with one master indicating This is the condition which is shown in Truth Table where CE
busy on one side of the array and another master indicating and SEM are both high.
busyononeothersideofthearray. Thiswouldinhibitthewrite
Systems which can best use the IDT7005 contain multiple
operations from one port for part of a word and inhibit the write processors or controllers and are typically very high-speed
operations from the other port for the other part of the word. systems which are software controlled or software intensive.
The busy arbitration, on a master, is based on the chip These systems can benefit from a performance increase
enableandaddresssignalsonly.Itignoreswhetheranaccess offered by the IDT7005's hardware semaphores, which pro-
is a read or write. In a master/slave array, both address and vide a lockout mechanism without requiring complex pro-
chip enable must be valid long enough for a busy flag to be gramming.
6.06
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
