IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2738 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
2738 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7005X15
Com'l. Only
IDT7005X17
Com'l. Only
IDT7005X20
IDT7005X25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
0
0
—
—
15
15
0
0
—
—
15
15
0
0
—
—
20
20
0
0
—
—
20
20
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
Interrupt Reset Time
IDT7005X35
IDT7005X55
IDT7005X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
25
25
0
0
—
—
40
40
0
0
—
—
50
50
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
Interrupt Reset Time
NOTE:
2738 tbl 16
1. "X" in part numbers indicates power rating (S or L).
6.06
14
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
