IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
t
WC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(3)
(4)
t
AS
tWR
R/W"A"
INT"B"
(3)
t
INS
2738 drw 17
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
t
INR
INT"B"
2738 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1,4)
Left Port
Right Port
OER A12R-A0R INTR
R/WL
CEL
L
OEL A12L-A0L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
1FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
1FFF
1FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
1FFE
X
X
X
Reset Left INTL Flag
NOTES:
2738 tbl 17
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.06
15
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
