ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Revision History
Rev. Originator Issue Date Description
1. Added Phase Noise Parameters, Updated input to output delay values.
2. PLL BW moved to PLL parameters table.
8/6/2007 3. Added terminations tables.
F
G
H
12/14/2007 Updated General SMBus Interface Information.
10/29/2008 Corrected "HCSL" typos.
1. Added I-temp electricals
2. Changed datasheet title
1/15/2010
J
3. Updated Input Frequency parameter
4. Updated ordering information
K
RW
4/1/2010 Updated ordering info for Rev B
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2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
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