ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
Number
1, 7, 12,
25, 30, 34
2, 3
4, 5
6, 16, 31
8, 9
10, 11
13
14
Name
Name
V
CCO
Q0, nQ0
Q1, nQ1
V
EE
Q2, nQ2
Q3, nQ3
MODE
Margin
Type
Type
Power
Ouput
Ouput
Power
Ouput
Ouput
Input
Input
Pulldown
Pulldown
Description
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
See Table 4B. LVCMOS/LVTTL interface levels.
Sets the frequency to ±5% in frequency margining mode.
See Table 1B. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go LOW and inver ted outputs
nQx to go HIGH. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
Reference input clock. LVCMOS/LVTTL interface levels.
Cr ystal select pin. Selects between the cr ystal and the reference
clock inputs. LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Core supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly
to the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
15
17
18
19,
20
21, 35
22
23, 24,
37, 38,
39, 40,
41, 42,
43, 44,
45, 46,
47, 48
26, 27
28 , 2 9
32, 33
36
MR
REF_CLK
nXTAL_SEL
XTAL_OUT,
XTAL_IN
V
CC
nPLL_SEL
SEL0, SEL1,
SEL2, SEL3,
SEL4, SEL5,
SEL6, SEL7,
SEL8, SEL9,
SEL10, SEL11,
SEL12, SEL13
Q4, nQ4
Q5, nQ5
Q6, nQ6
V
CCA
Input
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Pulldown
Input
Pullup
Output divider select pins. See Table 1A.
LVCMOS/LVTTL interface levels.
Ouput
Ouput
Ouput
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
4A. nXTAL_SEL C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
nXTAL_SEL
0
1
Selected Source
XTAL_IN, XTAL_OUT
REF_CLK
T
ABLE
4B. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
MODE
0
1
Condition
Q0:Q6, nQ0:nQ6
Default Mode
Frequency Margining Mode
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
3
ICS843207CY-350 REV. A DECEMBER 3, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
