ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
LVCMOS
TO
XTAL I
NTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in
Figure 3.
The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
VDD
R1
Ro
Rs
Zo = 50
.1uf
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
F
IGURE
3. G
ENERAL
D
IAGRAM FOR
LVCMOS D
RIVER TO
XTAL I
NPUT
I
NTERFACE
R
ECOMMENDATIONS FOR
U
NUSED
I
NPUT AND
O
UTPUT
P
INS
I
NPUTS
:
C
RYSTAL
I
NPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_CLK I
NPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS C
ONTROL
P
INS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
O
UTPUTS
:
LVPECL O
UTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
9
ICS843207CY-350 REV. A DECEMBER 3, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
