FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 3 2 0 7 - 3 5 0 i s a l ow p h a s e - n o i s e
IC
S
frequency margining synthesizer that targets
HiPerClockS™
clocking for high performance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
IDT. In the default mode, each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
F
EATURES
•
Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
•
Individual high impedance control of each output
•
Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
• Output frequency can be varied ± 5% from nominal
• VCO range: 620MHz - 750MHz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
33
4
5
32
48-Pin LQFP
6
7mm x 7mm x 1.4mm
31
package body
30
7
Y Package
8
29
Top View
9
28
27
10
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
SEL8
SEL9
SEL10
SEL11
SEL12
SEL13
V
CCO
Q0
nQ0
Q1
nQ1
V
EE
V
CCO
Q2
nQ2
Q3
nQ3
V
CCO
ICS843207-350
V
CCA
V
CC
V
CCO
nQ6
Q6
V
EE
V
CCO
nQ5
Q5
nQ4
Q4
V
CCO
B
LOCK
D
IAGRAM
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q0
nQ0
Pullup
2
SEL[1:0]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
Q1
nQ1
2
SEL[3:2]
Q2
nQ2
IDT
™
/ ICS
™
LVPECL FREQUENCY MARGINING SYNTHESIZER
REF_CLK
V
EE
MR
MARGIN
MODE
SEL1
SEL0
nPLL_SEL
V
CC
XTAL_IN
XTAL_OUT
nXTAL_SEL
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
nPLL_SEL
Pulldown
14MHz
2
SEL[5:4]
Q3
nQ3
XTAL_IN
OSC
1
0
0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
XTAL_OUT
REF_CLK
Pulldown
nXTAL_SEL
Pulldown
0
1
2
Predivider
÷2
1
Phase
Detector
SEL[7:6]
Q4
nQ4
VCO
620 - 750MHz
0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
÷50
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
2
SEL[9:8]
Q5
nQ5
1
÷95
÷105
MODE
Pulldown
MARGIN
Pulldown
MR
Pulldown
Pullup
2
SEL[11:10]
Q6
nQ6
To O/P Dividers
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pullup
2
SEL[13:12]
1
ICS843207CY-350 REV. A DECEMBER 3, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
