ICS342
Field Programmable Dual Output SS VersaClock
Parameter
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal pull-up resistor
Internal pull-down
resistor
Input Capacitance
Symbol
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUP
R
PD
C
IN
Conditions
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12mA
Min.
VDD-0.4
2.4
Typ.
Max.
Units
V
V
0.4
±70
20
V
mA
Ω
kΩ
kΩ
pF
SEL, PDTS pins
CLK output
Inputs
250
525
4
Note 1: Example with 25 MHz crystal input with two outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Power-up time
Symbol
F
IN
Conditions
Fundamental Crystal
Input Clock
Min.
5
2
0.25
Typ.
Max. Units
27
50
200
MHz
MHz
MHz
ns
ns
60
10
2
%
ms
ms
t
OR
t
OF
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
PLL lock time from
power-up, Note 3
PDTS goes high until
stable CLK output, Spread
Spectrum Off, Note 3
PDTS goes high until
stable CLK output, Spread
Spectrum On, Note 3
40
1
1
49-51
4
0.2
4
7
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Note 1: Measured with 15 pF load.
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
50
+200
ps
ps
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK2 for each PLL powered up. PDTS
transition high on select address change.
MDS 342 G
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 011205
tel (408) 297-1201
●
www.icst.com
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
