ICS342
Field Programmable Dual Output SS VersaClock
Pin Assignment
X1/ I CLK
VDD
GND
CLK1
1
2
3
4
8
7
6
5
X2
PDTS
SEL
CLK2
Output Clock Selection Table
SEL CLK1 (MHz) CLK2 (MHz)
0
1
User
Configurable
User
Configurable
User
Configurable
User
Configurable
Spread
Percentage
User
Configurable
User
Configurable
8-pin (150 mil) SOIC
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
VDD
GND
CLK1
CLK2
SEL
PDTS
X2
Pin
Type
XI
Power
Power
Output
Output
Input
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a crystal or external clock input.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Select for frequency selection on CLK1 and CLK2. Internal pull-up resistor.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up
resistor.
Connect this pin to a crystal, or float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS342 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
MDS 342 G
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 011205
tel (408) 297-1201
●
www.icst.com
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
