IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
Function Table1 Select Input Decoding
S2 S1
CLKA
CLKB
Output PLL Shut
Source
Down
L
L
L
H
L
Tri-state Tri-state
PLL
Y
N
Y
N
Driven
Driven
Driven
Tri-state
Driven
Driven
PLL
H
H
REF
PLL
H
Note 1: H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
Pin Name
REF1
CLKA12
CLKA22
VDD
Pin Description
1
2
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3 V Supply
3
4
5
GND
Ground
6
CLKB12
CLKB22
S23
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
7
8
9
S13
Select Input, Bit 1
10
11
12
13
14
15
16
CLKB32
CLKB42
GND
Clock Output for Bank B
Clock Output for Bank B
Ground
VDD
3.3 V Supply
CLKA32
CLKA42
FBK
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
IDT™ 3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
2
IDT2308B
REV B 030509
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
