IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Function Table
1
Select Input Decoding
S2
L
L
H
H
S1
L
H
L
H
CLKA
Tri-state
Driven
Driven
Driven
CLKB
Tri-state
Tri-state
Driven
Driven
Output
Source
PLL
PLL
REF
PLL
PLL Shut
Down
Y
N
Y
N
Note 1:
H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
1
CLKA1
2
CLKA2
2
VDD
GND
CLKB1
2
CLKB2
2
S2
3
S1
3
CLKB3
2
CLKB4
2
GND
VDD
CLKA3
2
CLKA4
2
FBK
Pin Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3 V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3 V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
2
IDT2308B
REV B 030509
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
