DATASHEET
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
Description
The IDT2308B is a high-speed phase-lock loop (PLL) clock
multiplier. It is designed to address high-speed clock
distribution and multiplication applications. The zero delay
is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10
to 133 MHz.
The IDT2308B has two banks of four outputs each that are
controlled via two select addresses. By proper selection of
input addresses, both banks can be put in tri-state mode. In
test mode, the PLL is turned off, and the input clock directly
drives the outputs for system testing purposes. In the
absence of an input clock, the IDT2308B enters power
down, and the outputs are tri-stated. In this mode, the
device will draw less than 25µA.
The IDT2308B is available in six unique configurations for
both prescaling and multiplication of the Input REF Clock.
(see Available Options table.)
The PLL is closed externally to provide more flexibility by
allowing the user to control the delay between the input
clock and the outputs.
IDT2308B
Features
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Phase-Lock Loop Clock Distribution for Applications
ranging from 10 MHz to 133 MHz operating frequency
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Distributes one clock input to two banks of four outputs
•
Separate output enable for each output bank
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External feedback (FBK) pin is used to synchronize the
outputs to the clock input
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Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1x, 2x, 4x output options (see Available Options table)
No external RC network required
Operates at 3.3 V V
DD
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial temperature
ranges
Block Diagram
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
1
IDT2308B
REV B 030509
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
