欢迎访问ic37.com |
会员登录 免费注册
发布采购

1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号1893CF的Datasheet PDF文件第83页浏览型号1893CF的Datasheet PDF文件第84页浏览型号1893CF的Datasheet PDF文件第85页浏览型号1893CF的Datasheet PDF文件第86页浏览型号1893CF的Datasheet PDF文件第88页浏览型号1893CF的Datasheet PDF文件第89页浏览型号1893CF的Datasheet PDF文件第90页浏览型号1893CF的Datasheet PDF文件第91页  
ICS1893AF Data Sheet - Release  
Chapter 8 Management Register Set  
8.12 Register 17: Quick Poll Detailed Status Register  
Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only  
register used to provide an STA with detailed status of the ICS1893AF operations. During reset, it is  
initialized to pre-defined default values.  
Note:  
1. For an explanation of acronyms used in Table 8-18, see Chapter 1, “Abbreviations and Acronyms”.  
2. Most of this register’s bits are latching high or latching low, which allows the ICS1893AF to capture and  
save the occurrence of an event for an STA to read. (For more information on latching high and latching  
low bits, see Section 8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)  
3. Although some of these status bits are redundant with other management registers, the ICS1893AF  
provides this group of bits to minimize the number of Serial Management Cycles required to collect the  
status data.  
Table 8-18. Quick Poll Detailed Status Register (register 17 [0x11])  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Ac-  
cess  
SF  
De- Hex  
fault  
17.15 Data rate  
17.14 Duplex  
10 Mbps  
Half duplex  
100 Mbps  
Full duplex  
RO  
RO  
RO  
0
17.13 Auto-Negotiation  
Progress Monitor Bit 2  
Reference Decode Table Reference Decode Table  
Reference Decode Table Reference Decode Table  
Reference Decode Table Reference Decode Table  
LMX  
17.12 Auto-Negotiation  
Progress Monitor Bit 1  
RO  
RO  
RO  
RO  
LMX  
LMX  
LH  
0
0
0
0
17.11 Auto-Negotiation  
Progress Monitor Bit 0  
0
17.10 100Base-TX signal  
lost  
Valid signal  
PLL locked  
Signal lost  
17.9  
100BasePLL Lock  
Error  
PLL failed to lock  
LH  
17.8  
17.7  
False Carrier detect  
Normal Carrier or Idle  
Valid symbols observed  
False Carrier  
RO  
RO  
LH  
LH  
0
0
Invalid symbol  
detected  
Invalid symbol received  
0
17.6  
17.5  
Halt Symbol detected No Halt Symbol received Halt Symbol received  
RO  
RO  
LH  
LH  
0
0
Premature End  
detected  
Normal data stream  
Stream contained two  
IDLE symbols  
17.4  
17.3  
Auto-Negotiation  
complete  
Auto-Negotiation in  
process  
Auto-Negotiation  
complete  
RO  
RO  
0
0
100Base-TX signal  
detect  
Signal present  
No signal present  
0
17.2  
17.1  
17.0  
Jabber detect  
Remote fault  
Link Status  
No jabber detected  
Jabber detected  
RO  
RO  
RO  
LH  
LH  
LL  
0
0
0
No remote fault detected Remote fault detected  
Link is not valid Link is valid  
ICS1893AF,
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
87