欢迎访问ic37.com |
会员登录 免费注册
发布采购

1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号1893CF的Datasheet PDF文件第81页浏览型号1893CF的Datasheet PDF文件第82页浏览型号1893CF的Datasheet PDF文件第83页浏览型号1893CF的Datasheet PDF文件第84页浏览型号1893CF的Datasheet PDF文件第86页浏览型号1893CF的Datasheet PDF文件第87页浏览型号1893CF的Datasheet PDF文件第88页浏览型号1893CF的Datasheet PDF文件第89页  
ICS1893AF Data Sheet - Release  
Chapter 8 Management Register Set  
8.11.1 Command Override Write Enable (bit 16.15)  
The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write  
(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW  
bit:  
1. Step one is to issue a Command Override Write, (that is, set bit 16.15 to logic one). This step enables  
the next MDIO write to have the ability to alter any CW bit.  
2. Step two is to write to the register that includes the CW bit which requires modification.  
Note: The Command Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic  
zero after the next MII write, thereby allowing only one subsequent write to alter the CW bits in a  
single register. To alter additional CW bits, the Command Override Write Enable bit must once  
again be set to logic one.  
8.11.2 ICS Reserved (bits 16.14:11)  
ICS is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.  
When one of these reserved bits is:  
Read by an STA, the ICS1893AF returns a logic zero.  
Written to by an STA, the STA must use the default value specified in this data sheet.  
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893AF,  
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write  
the default value of any reserved bits during all management register write operations.  
8.11.3 PHY Address (bits 16.10:6)  
These five bits hold the Serial Management Port Address of the ICS1893AF. During either a hardware  
reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED  
interface, see Section 6.5, “Status Interface” and Section 9.2.2, “Multi-Function (Multiplexed) Pins: PHY  
Address and LED Pins”). The PHY address is then latched into this register. (The value of each of the PHY  
Address bits is unaffected by a software reset.)  
8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)  
The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893AF to lose LOCK, thereby  
requiring the Stream Cipher Scrambler to resynchronize.  
8.11.5 ICS Reserved (bit 16.4)  
See Section 8.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.  
8.11.6 NRZ/NRZI Encoding (bit 16.3)  
This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on  
One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:  
Zero, the ICS1893AF encodes the serial transmit data stream using NRZ encoding.  
One, the ICS1893AF encodes the serial transmit data stream using NRZI encoding.  
ICS1893AF,
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
85  
 复制成功!