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1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1893AF Data Sheet - Release  
Chapter 6 Interface Overviews  
6.5 Status Interface  
The ICS1893AF provides five multi-function configuration pins that report the results of continual link  
monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 9.2.2.)  
Table 6-3. Pins for Monitoring the Data Link  
Pin  
P0AC  
LED Driven by the Pin’s Output Signal  
AC (Link Activity) LED  
P1CL  
P2LI  
CL (Collisions) LED  
LI (Link Integrity) LED  
P3TD  
P4RD  
TD (Transmit Data) LED  
RD (Receive Data) LED  
Note:  
1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input  
that is sampled when the ICS1893AF exits the reset state. After sampling is complete, these pins are  
output pins that can drive status LEDs.  
2. A software reset does not affect the state of a multi-function configuration pin. During a software reset,  
all multi-function configuration pins are outputs.  
3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the  
address of the ICS1893AF. LEDs may be placed in series with these resistors to provide a designated  
status indicator as described in Table 6-3.  
Caution: All pins listed in Table 6-3 must not float.  
4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled  
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For  
example, if a multi-function configuration pin is pulled down to ground through an LED and a  
current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the  
asserted state, the output is driven high.  
5. Adding 10Kresistors across the LEDs ensures the PHY address is fully defined during slow VDD  
power-ramp conditions.  
6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII  
tri-stated.)  
ICS1893AF,
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
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