ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.14 Register 19: Extended Control Register 2
The Extended Control Register provides more refined control of the internal ICS1892 operations.
Note:
1. For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 8-21. Extended Control Register (register [0x13])
Bit
Definition
When Bit = 0
When Bit = 1
Repeater mode
Software mode
Ac-
cess
SF
–
De-
fault
Hex
19.15 Node/Repeater Mode
Node mode
RO
RO
RO
NOD/
REP†
–
19.14 Hardware/Software
Mode
Hardware mode
–
HW/
SW†
19.13 Remote Fault
No faults detected
Remote fault
detected
–
0
19.12 ICS reserved
19.11 ICS reserved
19.10 ICS reserved
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
1
0
0
3
19.9
19.8
19.7
19.6
19.5
19.4
19.3
19.2
19.1
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
Automatic 10Base-T
Power Down
Do not automatically Power down
power down automatically
19.0
Automatic 100Base-TX
Power Down
Do not automatically Power down
power down automatically
RW
–
1
† The default is the state of this pin at reset.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
98
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
