ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.13.2 Polarity Reversed (bit 18.14)
The Polarity Reversed bit is used to inform an STA whether the ICS1892 has detected that the signals on
the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is:
• Correct, the ICS1892 sets bit 18.14 to a logic zero.
• Reversed, the ICS1892 sets bit 18.14 to logic one.
Note: The ICS1892 can detect this situation and perform all its operations normally, independent of the
reversal.
8.13.3 ICS Reserved (bits 18.13:6)
See Section 8.13.1, “ICS Reserved (bit 18.15)”, the text for which also applies here.
8.13.4 Jabber Inhibit (bit 18.5)
The Jabber Inhibit bit allows an STA to disable Jabber Detection. When an STA sets this bit to:
• Zero, the ICS1892 enables 10Base-T Jabber checking.
• One, the ICS1892 disables its check for a Jabber condition during data transmission.
8.13.5 ICS Reserved (bit 18.4)
See Section 8.13.1, “ICS Reserved (bit 18.15)”, the text for which also applies here.
8.13.6 Auto Polarity Inhibit (bit 18.3)
The Auto Polarity Inhibit bit allows an STA to prevent the automatic correction of a polarity reversal on the
Twisted-Pair Receive pins (TP_RXP and TP_RXN). If an STA sets this bit to logic:
• Zero (the default), the ICS1892 automatically corrects a polarity reversal on the Twisted-Pair Receive
pins.
• One, the ICS1892 either disables or inhibits the automatic correction of reversed Twisted-Pair Receive
pins.
Note: This bit is also used to correct a reversed signal polarity for 100Base-TX operations.
8.13.7 SQE Test Inhibit (bit 18.2)
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
• Zero, the ICS1892 enables its SQE Test generation.
• One, the ICS1892 disables its SQE Test generation.
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
functionality of this bit.
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
inhibiting of the SQE test in full-duplex mode or repeater mode.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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