ICS1892
TSD
Chapter 6 Interface Overviews
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
6.2 100M Symbol Interface
The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for
which the repeater requires only recovered parallel data and for which the repeater provides all the
necessary framing and control functions.
When the Mac/Repeater Interface is configured for 100M Symbol operations, the ICS1892 and the
MAC/repeater exchange unframed 5-bit, parallel symbols at a 25-MHz clock rate.
The ICS1892 configuration functions determine the operation of the MAC/Repeater Interface. The
configuration functions are controlled by either input pins (in which case, the HW/SW pin is logic zero to
select the hardware mode) or Management Register bits (in which case, the HW/SW pin is logic one to
select the software mode).
• In hardware mode, the ICS1892 enables the 100M Symbol Interface when both of the following are true:
– The MII/SI input pin is logic one (that is, the selection is for the Symbol Interface).
– The 10/100SEL input pin is logic one (that is, the selection is for 100M operations).
• In software mode, the ICS1892 enables the 100M Symbol Interface when both the following are true:
– The MII/SI input pin is logic one (that is, the selection is for the Symbol Interface).
– The Control Register Data Rate bit (bit 0.13) is set to logic one (that is, the selection is for selecting
100M operations)
Note: In software mode, the 10/100SEL pin becomes an output that indicates the state of bit 0.13.
The 100M Symbol Interface bypasses the ICS1892 PCS and provides a direct unscrambled, unframed,
5-bit interface between the MAC/repeater and the PMA sublayer. A benefit of bypassing the PCS is a
reduction in the latency through the ICS1892. That is, when the ICS1892 MAC/Repeater Interface is
configured as a 100M Symbol Interface, the bit delays through the ICS1892 are smaller than the standard
MII Data Interface can allow. The ICS1892 provides this 100M Symbol Interface primarily for Repeater
applications, for which latency is a critical performance parameter.
In addition to the exchange of symbol data, the ICS1892 provides ISO/IEC-compliant control signals (such
as CRS) to the MAC/repeater. The ICS1892 CRS signal provides a fast look-ahead, which can benefit a
repeater application.
In the 100M Symbol Interface mode, the ICS1892 continues to assert the CRS signal using its PCS logic.
This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received
from the PMA sublayer serially. In fact, because the PCS CRS does not wait for a nibble or symbol to be
constructed, the PCS CRS is available in advance of the symbol generation. Therefore, by employing the
PCS CRS generation logic, the ICS1892 can provide an ‘early’ indication of a Carrier Detect to the
MAC/repeater.
The 100M Symbol Interface consists of the following fourteen signals: STCLK, STD[4:0], SRCLK,
SRD[4:0], SCRS, and SD. (When the ICS1892 MAC/Repeater Interface is configured for 100M Symbol
operations, its default MII pin names and their associated functions are redefined. For more information,
see Section 9.2.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface”.)
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
