ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 6 Interface Overviews
ICS1892 Data Sheet
6.1 MII Data Interface
The most common configuration for the ICS1892 MAC/Repeater Interface is to configure the
MAC/Repeater Interface as a Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps
(depending on the configuration). When the MAC/Repeater Interface is configured for the MII Data
Interface mode, the MAC/Repeater Interface is used to transfer between the ICS1892 and the
MAC/repeater framed, 4-bit parallel nibbles, along with control and status signals.
The ICS1892 implements an MII that is fully compliant with the IEEE Std 802.3u when connecting to MACs
or repeaters. The ICS1892 MII supports a variety of interfaces to MACs and repeaters, which can occur as
follows:
• On the same board (that is chip to chip)
• On a motherboard to a daughterboard
• Through an MII connector and cable (in a manner similar to AUI connections)
Clause 22 of the ISO/IEC standard defines the MII between an Ethernet PHY and the MAC/Reconciliation
sublayer for 10-Mbps and 100-Mbps operations. The specification supports a variety of physical media,
including 100Base-TX, 100Base-T4, and 100Base-FX. The specification is such that use of a specific
medium for the Link Segment is transparent to the MAC. The ICS1892 supports this definition for both
100Base-TX and 10Base-T operations.
The ISO/IEC-specified MII has both a transmit and a receive data path. Each data path can synchronously
exchange 4 bits of data (that is, nibbles).
• The transmit data path includes the following:
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
• The receive data path includes the following:
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
Both the transmit clock and the receive clock are provided to the MAC/Reconciliation sublayer by the
ICS1892 (that is, the ICS1892 sources the TXCLK and RXCLK signals).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICS1892 is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
• Half-duplex mode, the ICS1892 asserts the Carrier Sense signal when data is being either transmitted or
received. While operating in half-duplex mode, the ICS1892 also asserts the Collision Detect signal to
indicate that data is being received while a transmission is in progress.
• Full-duplex mode, the ICS1892 asserts the Carrier Sense signal only when receiving data and forces the
Collision Detect signal to remain inactive.
As mentioned in Section 5.1.1.3, “Hot Insertion”, the ICS1892 design allows hot insertion of its MII. That is,
it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1892 isolates its MII signals and tri-states the signals on the Twisted-Pair Transmit
pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the ICS1892
enables its MII and enables its Twisted-Pair Transmit signals.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
