ICS1522
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
ICS1522
TSD
REG#
4
BIT(S)
3-5
BIT REF.
PFD (0;2)
DESCRIPTION
Phase Frequency Detector Gain
PFD(2)
PFD(1)
PFD(0)
PFD GAIN
FINE PHASE
ADJ.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
.2344uA/2
Π
rad
.9375uA/2
Π
rad
3.750uA/2
Π
rad
15.00uA/2
Π
rad
1.875uA/2
Π
rad
7.500uA/2
Π
rad
30.00uA/2
Π
rad
120.0uA/2
Π
rad
3ns/V
3ns/V
3ns/V
3ns/V
6ns/V
6ns/V
1.5ns/V
.375ns/V
4
6
PDEN
Phase Frequency Detector Enable
(Default=1) 0=PFD Disable; 1=PFD Enable
Loop Filter Select (Default=1)
0=External Loop Filter (IPUMP & VVCO active)
1=Internal Loop Filter
VCO Select (Default=1)
0=External VCO (EXTVCO active)
1=Internal VCO
Feedback Divider Clock Input Select (Default=0)
0=VCO; 1=OUT1
Must be set to one.
Feedback Select (Default=1)
0=External Feedback (EXTFBK active)
1=Internal Feedback An active external feedback signal at EXTFBK
is necessary to synchronously switch to internal.
External Feedback Polarity (Default=0)
0=Positive Edge; 1=Negative Edge
Addition of 1 VCO Cycle (Default=0)
Toggle (0 to 1 to 0) to add 1 VCO cycle.
Removal of 1 VCO Cycle (Default=0)
Toggle (0 to 1 to 0) to remove 1 VCO cycle.
4
7
INT_FLT
4
8
INT_VCO
4
9
CLK_SEL
4
5
10
0
RESERVED
FBK_SEL
5
1
FBK_POL
5
2
ADD
5
3
SWLW
6
IDT™ / ICS™
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
6
ICS1522
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
