ICS1522
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
ICS1522
TSD
Output Description
The differential output drivers,
CLK+
and
CLK-,
are
current-mode and are designed to drive resistive terminations
in a complementary fashion. The outputs are current-
sinking only, with the amount of sink current programmable
via the
IPRG
pin. The sink current, which is steered to
either
CLK+
or
CLK-,
is four times the current supplied to
the
IPRG
pin. For most applications, a resistor from VDDO
to IPRG will set the current to the necessary precision.
Reference Oscillator and
Crystal Selection
The
ICS1522
has circuitry on-board to implement a Pierce
oscillator with the addition of a quartz crystal and two
external loading capacitors (EXTREF bit must be set to
logic 0). Pierce oscillators operate the crystal in anti- (also
called parallel-) resonant mode.
Series-resonant crystals may also be used with the
ICS1522.
Be aware that the oscillation frequency will be slightly
higher than the frequency that is stamped on the can
(typically 0.025-0.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the
ICS1522
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the
ICS1522,
it is important that it be jitter-free. The rising
and falling edges of that signal should be fast and free of
noise for best results. The loop phase is locked to the rising
edge of the XTAL1/EXTREF input signal, if REF_POL is
set to logic 0. Additionally, the EXTREF bit should be set
to logic 1 to switch in a TTL-compatible buffer at this
input.
Line-Locked Operation
Some video applications require a clock to be generated
that is a multiple of horizontal sync. The
ICS1522
supports this mode of operation. The reference divider
should be set to divide by one and the desired polarity
(rising or falling) of lock edge should be selected. By
using the phase detector hardware disable mode (PDEN),
the PLL can be made to free-run at the beginning of the
vertical interval of the external video, and can be
reactivated at its completion.
External Feedback Operation
The
ICS1522
option also supports the inclusion of an
external counter as the feedback divider of the PLL.
This mode is useful in graphic systems that must be
“genlocked” to external video sources.
When the FBK_SEL bit is set to logic 0, the phase-
frequency detector will use the
EXTFBK
pin as its
feedback input. The loop phase will be locked to the
rising edges of the signal applied to the EXTFBK input
if FBK_POL is set to logic 0 Synchronous switchover
to the internal feedback can be ac-complished by
setting the FBK-SEL bit to logic 1 while an active
feedback source exists on the EXTFBK pin.
24-Pin SOIC
Fine Phase Adjustment
The
ICS1522
has the capability of adjusting the pixel
clock phase relative to the input reference phase.
Entire pixels can be added or removed under register
control with sub-pixel adjust-ment accomplished by a
control voltage on the FINE input pin. By utilizing the
fine phase adjust, after first synchronously switching
from external feedback to internal feedback, the graphics
system phase can be precisely controlled relative to
the input horizontal sync.
3
IDT™ / ICS™
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator
3
ICS1522
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
