IC62C1024AL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
t
HD
t
SD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Vcc for Data Retention
TestCondition
See Data Retention Waveform
Min.
2.0
Max.
5.5
Unit
V
IDR
Data Retention Current
Vcc = 3.0V, CE1 > Vcc – 0.2V
Com.
Ind.
—
—
250
400
µA
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
—
ns
ns
tRC
DATA RETENTION WAVEFORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
V
V
CC
DR
5.0V
3.0V
CE1 ≥ V
CC
- 0.2V
CE1
GND
8
Integrated Circuit Solution Inc.
ALSR009-0A 5/7/2002
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
