IC42S16100
Write Cycle / Ping-Pong Operation (Bank Switching)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
ROW
ROW
ROW
ROW
ROW
COLUMN
COLUMN
A0-A9
AUTO PRE
AUTO PRE
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
NO PRE
BANK 0
BANK 0 OR 1
BANK 0
t
AS
BANK 0
BANK 1
BANK 0
BANK 1
t
CH
t
CS
DQM
I/O
t
DS
t
DS
t
DS
t
DS
t
DS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
tDH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
t
DPL
tDPL
(BANK 0)
t
t
RCD
t
RCD
RAS
(BANK 1)
t
RP
t
RAS
t
(BANK 0)
(BANK 0)
t
RC
t
RC
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<
ACT 0>
<ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
WRITA 1>
>
<PRE 0
>
<ACT 0>
<
>
<
Undefined
Don’t Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don't Care.
66
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
