IC42S16100
Write Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN
NO PRE
BANK 0
ROW
ROW
A0-A9
t
t
AH
AH
A10
A11
BANK 0 OR 1
BANK 0
t
AS
BANK 0
t
CH
t
CS
DQM
I/O
t
DH
tDS
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
D
IN 0m
D
IN 0m+2
D
IN 0m-1
DIN 0m
D
IN 0m+1
t
RCD
tDPL
t
RAS
RC
tRP
t
<BST
>
<PRE 0>
<
ACT 0>
<WRIT0>
Undefined
Don’t Care
CAS latency = 3, burst length = full page
Note 1: A8,A9 = Don't Care.
Integrated Circuit Solution Inc.
65
DR024-0D 06/25/2004