IC41C16100S
IC41LV16100S
TRUTH TABLE
Function
RAS
LCAS UCAS
WE
X
OE
X
Address tR/tC I/O
Standby
Read: Word
Read: Lower Byte
H
L
L
H
L
L
H
L
H
X
High-Z
H
L
ROW/COL
ROW/COL
DOUT
H
L
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L
L
L
L
L
H
L
L
X
X
ROW/COL
ROW/COL
DIN
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H
→
L
L
→
H
DOUT, DIN
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
L
L
L
H
→
L
L
H
→
L
L
H
H
H
L
L
L
ROW/COL
NA/COL
NA/NA
DOUT
DOUT
DOUT
H
→
→
→
→
→
→
H
→
→
→
→
→
→
Any Cycle:
L
H
L
H
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
L
H
L
H
L
L
X
ROW/COL
DIN
L
H
L
H
L
L
X
NA/COL
DIN
EDO Page-Mode(1,2)
Read-Write
1st Cycle:
L
L
H
L
H
L
H
→
L
L
L
→
H
H
ROW/COL
NA/COL
DOUT, DIN
DOUT, DIN
2nd Cycle:
H
L
H
L
H
→
L
→
Hidden Refresh
Read(2)
L
→
H
→
L
L
L
L
H
L
L
L
H
L
H
L
X
X
L
ROW/COL
DOUT
Write(1,3)
L
→
H
→
X
ROW/COL
DOUT
RAS-Only Refresh
L
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh(4)
H
→
L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
4
Integrated Circuit Solution Inc.
DR010-0D 11/26/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
