IC41C16100S
IC41LV16100S
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ≤ VIN ≤ Vcc
–5
–5
2.4
—
5
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
5
µA
V
0V ≤ VOUT ≤ Vcc
VOH
VOL
ICC1
IOH = –5.0 mA (5V)
—
0.4
IOH = –2.0 mA (3.3V)
IOL = 4.2 mA (5V)
V
IOL = 2.0 mA (3.3V)
RAS, LCAS, UCAS ≥ VIH Commerical 5V
—
—
—
—
2
1
3
2
mA
mA
3.3V
Extended
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V
3.3V
ICC2
ICC3
Standby Current: CMOS
5V
—
—
1
mA
mA
3.3V
0.5
Operating Current:
RAS, LCAS, UCAS,
-45
-50
-60
—
—
—
190
160
145
Random Read/Write(2,3,4)
Average Power Supply Current
Address Cycling, tRC = tRC (min.)
ICC4
ICC5
ICC6
Operating Current:
RAS = VIL, LCAS, UCAS,
-45
-50
-60
—
—
—
100
90
mA
mA
mA
µA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
80
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
-45
-50
-60
—
—
—
180
160
145
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
Refresh Current:
RAS, LCAS, UCAS Cycling
-45
-50
-60
—
—
—
180
160
145
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
ICCS
Self Refresh Current
Self Refresh mode
—
—
300
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
7
DR010-0D 11/26/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
