ICS91857
Switching Characteristics for DDRI-400
PARAMETER
SYMBOL
CONDITION
MIN
TYP
3.5
MAX UNITS
ns
Low-to high level
1
CLK_IN to any output
tPLH
propagation delay time
High-to low level propagation
delay time
1
CLK_IN to any output
3.5
ns
tPLL
Output enable time
Output disable time
tEN
tdis
PD# to any output
PD# to any output
100 - 200 MHz
3
3
ns
ns
Period jitter
Tjit (per)
t(jit_hper)
t(sir_I)
-50
-75
1
50
75
4
ps
Half-period jitter
100 - 200 MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Static Phase Offset
Output to Output Skew
Pulse skew
V/ns
V/ns
ps
t(sl_o)
1
2
Tcyc-Tcyc
100 - 200 MHz
-75
-50
75
50
75
100
3
0
ps
t(spo)
Tskew
ps
Tskewp
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
0494C—08/15/05
8
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
