欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICS1893BYI-10LF 参数 Datasheet PDF下载

ICS1893BYI-10LF图片预览
型号: ICS1893BYI-10LF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用:
文件页数/大小: 143 页 / 1665 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS1893BYI-10LF的Datasheet PDF文件第13页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第14页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第15页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第16页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第18页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第19页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第20页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第21页  
ICS1893BY-10 - Release  
Chapter 4 Operating Modes Overview  
4.1 Reset Operations  
This section first discusses reset operations in general and then specific ways in which the ICS1893BY-10  
can be configured for various reset options.  
4.1.1 General Reset Operations  
The following reset operations apply to all the specific ways in which the ICS1893BY-10 can be reset,  
which are discussed in Section 4.1.2, “Specific Reset Operations”.  
4.1.1.1 Entering Reset  
When the ICS1893BY-10 enters a reset condition (either through hardware, power-on reset, or software), it  
does the following:  
1. Isolates the MAC/Repeater Interface input pins  
2. Drives all MAC/Repeater Interface output pins low  
3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)  
4. Initializes all its internal modules and state machines to their default states  
5. Enters the power-down state  
6. Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management  
Register bits to their default values  
4.1.1.2 Exiting Reset  
When the ICS1893BY-10 exits a reset condition, it does the following:  
1. Exits the power-down state  
2. Latches the Serial Management Port Address of the ICS1893BY-10 into the Extended Control  
Register, bits 16.10:6. [See Section 7.11.3, “PHY Address (bits 16.10:6)”.]  
3. Enables all its internal modules and state machines  
4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their  
associated ICS1893BY-10 input pins, as determined by the HW/SW pin  
5. Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)  
6. Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock  
(TXCLK) and receive clock (RXCLK)  
7. Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition  
is removed  
4.1.1.3 Hot Insertion  
As with the ICS189X products, the ICS1893BY-10 reset design supports ‘hot insertion’ of its MII. (That is,  
the ICS1893BY-10 can connect its MAC/Repeater Interface to a MAC/repeater while power is already  
applied to the MAC/repeater.)  
ICS1893BY-10 Rev A 3/24/04  
March, 2004  
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
17  
 复制成功!