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ICS1893CK 参数 Datasheet PDF下载

ICS1893CK图片预览
型号: ICS1893CK
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceive [3.3-V 10Base-T/100Base-TX Integrated PHYceive]
分类和应用: 电信集成电路
文件页数/大小: 126 页 / 1927 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1893CF Data Sheet Rev. F - Release  
Chapter 6 Functional Blocks  
6. To indicate that the auto-negotiation process is complete, the ICS1893CF sets bits 1.5 and 17.4 high to  
logic one. After successful completion of the auto-negotiation process, the ICS1893CF  
Auto-Negotiation sublayer performs the following steps:  
a. It sets to logic one the Status Register’s Auto-Negotiation Complete bit (bit 1.5, which is also  
available in the QuickPoll register as bit 17.4).  
b. It enables the negotiated link technology (such as the 100Base Transmit modules and 100Base  
Receive modules).  
c. It disables the unused technologies to reduce the overall power consumption.  
6.2.2 Auto-Negotiation: Parallel Detection  
The ICS1893CF supports parallel detection. It is therefore compatible with networks that do not support the  
auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link  
partners as well as 100Base-TX link partners that do not have an auto-negotiation capability.  
The Auto-Negotiation sublayer performs this parallel detection function when it does not get a response to  
its FLP bursts. In these situations, the Auto-Negotiation sublayer performs the following steps:  
1. It sets the LP_AutoNeg_Able bit (bit 6.0) to logic zero, thereby identifying the remote link partner as not  
being capable of executing the auto-negotiation process.  
2. It sets the bit in the Auto-Negotiation Link Partner Abilities Register that corresponds to the 'parallel  
detected' technology [for example, half-duplex, 10Base-T (bit 5.5) or half-duplex, 100Base-TX (bit  
5.7)].  
3. It sets the Status Register’s Auto-Negotiation Complete bit (bit 1.5) to logic one, indicating completion  
of the auto-negotiation process.  
4. It enables the detected link technology and disables the unused technologies.  
A remote link partner that does not support the auto-negotiation process does not respond to the  
transmitted FLP bursts. The ICS1893CF detects this situation and responds according to the data it  
receives. The ICS1893CF can receive one of five potential responses to the FLP bursts it is transmitting:  
FLP bursts, 10Base-T link pulses (that is, Normal Link Pulses), scrambled 100Base IDLEs, nothing, or a  
combination of signal types.  
A 10Base-T link partner transmits only Normal Link Pulses when idle. When the ICS1893CF receives  
Normal Link Pulses, it concludes that the remote link partner is a device that can use only 10Base-T  
technology. A 100Base-TX node without an Auto-Negotiation sublayer transmits 100M scrambled IDLE  
symbols in response to the FLP bursts. Upon receipt of the scrambled IDLEs, the ICS1893CF concludes  
that its remote link partner is a 100Base-TX node that does not support the auto-negotiation process. For  
both 10Base-T and 100Base-TX nodes without an Auto-Negotiation sublayer, the ICS1893CF clears bit 6.0  
to logic zero, indicating that the link partner cannot perform the auto-negotiation process.  
If the remote link partner responds to the FLP bursts with FLP bursts, then the link partner is a 100Base-TX  
node that can support the auto-negotiation process. In this case, the ICS1893CF sets to logic one the  
Auto-Negotiation Expansion Register’s Link Partner Auto-Negotiation Ability bit (bit 6.0).  
If the Auto-Negotiation sublayer does not receive any signal when monitoring the receive channel, then the  
QuickPoll Detailed Status Register’s Signal Detect bit (bit 17.3) is set to logic one, indicating that no signal  
is present.  
Another possibility is that the ICS1893CF senses that it is receiving multiple technology indications. In this  
situation, the ICS1893CF cannot determine which technology to enable. It informs the STA of this problem  
by setting to logic one the Auto-Negotiation Expansion Register’s Parallel Detection Fault bit (bit 6.4).  
ICS1893CF, Rev. F, 03/01/07  
Mar. 2007  
Copyright © 2007, Integrated Device Technology, Inc.  
All rights reserved.  
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