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ICS1574BM 参数 Datasheet PDF下载

ICS1574BM图片预览
型号: ICS1574BM
PDF下载: 下载PDF文件 查看货源
内容描述: 用户可编程的激光引擎像素时钟发生器 [User Programmable Laser Engine Pixel Clock Generator]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 12 页 / 188 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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ICS1574B
Power Supplies and Decoupling
The
ICS1574B
has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the PCB as close to
the package as is possible.
The
ICS1574B
has a VDDO pin which is the supply of +5
volt power to the output driver. This pin should be con-
nected to the power plane (or bus) using standard
high-frequency decoupling practice. That is, capacitors
should have low series inductance and be mounted close to
the
ICS1574B.
The VDD pin is the power supply pin for the PLL synthe-
sizer circuitry and other lower current digital functions.
We recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended appli-
cation circuitry). This will allow the PLL to “track”
through power supply fluctuations without visible effects.
See Figure 4 for typical external circuitry.
Figure 4
6