ICS1574B
Register Mapping — ICS1574B
NOTE:
It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
1–4
BIT REF.
PCLK[0]..PCLK[3]
DESCRIPTION
Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
PCLK[ 3]
0
0
0
0
0
0
0
0
1
1
1
1
PCLK[ 2]
0
0
0
0
1
1
1
1
X
X
X
X
PCLK[ 1]
0
0
1
1
0
0
1
1
0
0
1
1
PCLK[ 0]
0
1
0
1
0
1
0
1
0
1
0
1
MODUL US
3
4( a )
4( b)
5
6
8( a )
8( b)
10
12
16( a )
16( b)
20
(X =
Don't Care
)
5, 6
7
8
Reserved
Reserved
SELXTAL
Must be set to 0.
Must be set to 1.
Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
Must be set to 0.
Must be set to 1.
Must be set to 0.
PLL post-scaler / test mode select bits.
S[1]
0
0
1
1
S[0]
0
1
0
1
DESCRI PTI ON
Post-scaler = 1. F(CLK) = F(PLL). The output of the PCLK
divider drives the PCLK output.
Post-scaler = 2. F(CLK) = F(PLL)/2. The output of the
PCLK divider drives the PCLK output.
Post-scaler = 4. F(CLK) = F(PLL)/4. The output of the
PCLK divider drives the PCLK output.
AUX-EN TEST MODE. The AUX_PCL
K
bit drives the
PCLK output.
9
10
11, 12
13 – 14
Reserved
Reserved
Reserved
S[0]..S[1]
7
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