ICS1574B
Pin Configuration
PCLKEN
XTAL1
XTAL2
DATCLK
VSS
VSS
PCLK
(Do Not Connect)
Reserved
1
2
16
15
DATA
HOLD
TEST
(Connect to VSS))
VDD
VDDO
Reserved
(Do Not Connect)
Reserved
(Do Not Connect)
Reserved
(Do Not Connect)
ICS1574B
3
4
5
6
7
8
14
13
12
11
10
9
16-Pin Skinny SOIC
Pin Descriptions
PIN NUMBER
7
1
2
3
4
16
15
14
8, 9, 10, 11
13
12
5, 6
P I N NA M E
PCLK
PCLKEN
X TA L 1
X TA L 2
DAT C L K
DATA
HOLD
Te s t
R e s e r ve d
VDD
VDDO
VSS
DESCRIPTION
P i xe l c l o c k o u t p u t .
PCLK Enable (Input).
Q u a r t z c r y s t a l c o n n e c t i o n 1 / ex t e r n a l r e f e r e n c e f r e q u e n cy i n p u t .
Quartz crystal connection 2.
Data Clock (Input).
S e r i a l R eg i s t e r D a t a ( I n p u t ) .
HOLD (Input).
Test. (Must be connected to VSS.)
R e s e r ve d . ( D o N o t C o n n e c t . )
PLL system power (+5V. See application diagram).
Output stage power (+5V).
Device ground. (Both pins must be connected.)
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
