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ICS1531 参数 Datasheet PDF下载

ICS1531图片预览
型号: ICS1531
PDF下载: 下载PDF文件 查看货源
内容描述: 888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用: 转换器时钟发生器
文件页数/大小: 76 页 / 525 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1531 Data Sheet - Preliminary  
Chapter 2 Summary  
Chapter 2 Summary  
2.1 Overview  
The ICS1531 addresses stringent display system line-locked applications by providing clock signals and  
digitized pixel data through internal high-performance analog-to-digital converters (ADCs). The ICS1531 is  
a complete solution for capturing analog red, green, and blue (RGB) signals from personal computers and  
workstations. It supports data capture for resolutions from VGA (640 × 480) to UXGA (1600 × 1200). The  
ICS1531 features are described in the following sections.  
2.2 Clamp, Video Amplifier, and Analog-to-Digital Circuits (Condition RGB Inputs)  
For the following circuits, see Figure 4-3.  
2.2.1 Clamp Circuits (Adjust RGB Inputs to ADC Range)  
To properly digitize incoming RGB analog signals, the ICS1531 must adjust the signals to the range of the  
ADC. This adjustment is done by clamping the signal, which both (1) establishes a bottom voltage limit and  
(2) offsets the signal to align the black level of the incoming signal with the bottom voltage limit. Then the  
signal is amplified to adjust the top limit to the upper range of the ADC.  
The ICS1531 incorporates an internal clamping circuit to generate a clamping signal. Optionally, the  
CLAMP pin can be used to input an externally generated clamp signal (Reg 30:2). In either case, the  
polarity of the signal to a clamp can be programmed (Reg 30:3). Typically, the clamp signal is generated by  
ADCSYNC (the recovered HSYNC timing pulse). The clamp signal is generated during a non-display  
region of time, when most PC display controllers output a black signal.  
2.2.2 Video Amplifier Circuits (Amplify RGB Inputs)  
The ICS1531’s video amplifier circuit can directly accept analog RGB input signals from a PC display  
controller (that is, no external pre-amplifier is required). The video amplifier circuit has three independent  
500-MHz video amplifiers for the RGB inputs. To adjust the top level of the signal, this video amplifier circuit  
can be programmed for a gain of 1.0, 1.2, 1.4, or 1.6 (Regs 31:1-0, 32:1-0, and 33:1-0). As a result, the  
video amplifier circuit can improve low-amplitude signals and adjust analog input signals for the optimum  
sampling range of the ADC circuit.  
2.2.3 Analog-to-Digital Circuits (Digitize RGB Inputs)  
The ICS1531 has high-performance analog-to-digital converters (ADCs) to capture and digitize analog  
RGB data (Reg 30:7). Low-power CMOS technology is used to create 8-bit ADCs, which are calibrated to  
align the capture event between (1) the 3 analog input channels and (2) either 3 or 6 digital output  
channels. The ADC can provide (through Reg 30:6) one of the following:  
Two 24-bit pixels aligned to a half-rate pixel clock (two-pixels-per-clock mode), which can be used for  
48-bit interface panels and image-scaling chips  
One 24-bit pixel aligned to a full-rate pixel clock (one-pixel-per-clock mode), which can be used for  
24-bit-per-pixel applications  
In addition, programmable digital-to-analog converters for the R, G, and B inputs fine-tune VRTR, VRTG,  
and VRTB, the individual R, G, and B maximum reference ‘top’ voltages (Regs 34-36).  
ICS1531 Rev N 12/1/99  
December, 1999  
Copyright © 1999, Integrated Circuit Systems, Inc.  
All rights reserved.  
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